USB 2.0 Full High Speed Solution | NXP Semiconductors
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP with M31 28nm PHY | audioXpress
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB3300 USB HS Board Host OTG PHY Low Pin ULPI Evaluation Development Module Kit|Computer Cables & Connectors| - AliExpress
USB 3.0 PHY for SoC Designs | Cadence IP
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB 3.0 PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
USB3300 USB HS Board Host OTG PHY Low Pin ULPI Evaluation Development Module Kit|Integrated Circuits| - AliExpress
TUSB1210-Q1 data sheet, product information and support | TI.com
ULPI - Kcchao
USB 2.0 Full High Speed Solution | NXP Semiconductors
PhyWhisperer-USB - NewAE Hardware Product Documentation
USB Component: USB Device
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
USB 2.0 PHY for SoC Designs | Cadence IP
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
The USB 2.0 Device IP core | Arasan Chip Systems
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
PCIe/USB/SATA PHY Appilcation example | Renesas
DE10-Advance Hardware Manual revC Chapter5 USB OTG - Terasic Wiki
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
